The present disclosure is related to a digital-to-analog converter and a code mapping method applied to the digital-to-analog converter, and more particularly, to a digital-to-analog converter which integrates a switched capacitor circuit and a direct-charge transfer circuit into its architecture and related code mapping method.
A digital-to-analog converter (DAC) is a common circuit element in various electronic devices and can generate an analog output voltage for application to back-end circuits according to a digital input value. Traditionally, a high speed DAC circuit is implemented by a current steering DAC architecture. Although the current steering DAC architecture has an advantage of high speed, it also has disadvantages of occupying area and high power consumption. Thus, it is only suitable for applications of lower than 10 bits and higher than 100 MHz, and is not suitable for applications for low power consumption.
As regards applications for low power consumption, a switched capacitor (SC) DAC architecture or an SC DAC collocating with an R-string sub DAC architecture can give consideration to performance, area, and power consumption. However, the performance of this architecture is restricted to the slew-rate of the operational amplifier (OPA). A direct charge transfer SC DAC architecture can solve the abovementioned slew-rate problem, but it needs more capacitors than the SC DAC collocating with the R-string sub DAC architecture if they have the same number of quantized levels. Hence, in order to simultaneously possess all the abovementioned advantages without increasing the number of capacitors within the DAC architecture, the existing DAC architectures need to be improved.